Central processing unit

Results: 2609



#Item
491Mathematics / Abstract algebra / Linear algebra / Central processing unit / Computer architecture / Vector processor / Superscalar / Cray-1 / Very long instruction word / Algebra / Parallel computing / Computing

Lecture 7: Vector Processing Professor David A. Patterson Computer Science 252 Spring 1998

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Source URL: www.cs.berkeley.edu

Language: English - Date: 1998-02-13 14:52:32
492Parallel computing / Central processing unit / GPGPU / Nvidia / Thread / Vectorization / Parallel Thread Execution / CUDA / SIMD / Computing / Concurrent computing / Computer architecture

Dynamic Compilation of Data-Parallel Kernels for Vector Processors Andrew Kerr1 , Gregory Diamos2 , S. Yalamanchili3 School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta, GA

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Source URL: www.gdiamos.net

Language: English - Date: 2012-03-06 12:51:51
493Automatic parallelization / Multi-core processor / Speedup / Thread / Lock / Task parallelism / Central processing unit / Data parallelism / OpenMP / Parallel computing / Computing / Computer programming

Microsoft Word - Final_Interact11.doc

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Source URL: www.eembc.org

Language: English - Date: 2013-04-08 17:03:50
494Parallel computing / Central processing unit / Computer memory / Classes of computers / CPU cache / Benchmark / Vector processor / Memory bandwidth / Cell / Computing / Computer hardware / Computer architecture

Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines Brian R. Gaeke1, Parry Husbands2, Xiaoye S. Li2, Leonid Oliker2, Katherine A. Yelick1,2, and Rupak Biswas3 1 Computer Science Division, University of California

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Source URL: iram.cs.berkeley.edu

Language: English - Date: 2003-01-09 09:13:00
495Central processing unit / Addressing mode / Machine code / Instruction set / Branch predication / Computer architecture / Instruction set architectures / Assembly languages

Microsoft Word - IHD_OS_Vol 4_Part 2_July_28_10.doc

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Source URL: files.renderingpipeline.com

Language: English - Date: 2013-09-24 10:33:32
496Central processing unit / Instruction set architectures / Virtual memory / Computer memory / Memory management unit / SuperH / CPU cache / Reduced instruction set computing / Addressing mode / Computer architecture / Computer hardware / Computing

SuperH™ (SH) 32-Bit RISC MCU/MPU Series SH7750 High-Performance RISC Engine Programming Manual

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Source URL: www.boob.co.uk

Language: English - Date: 2001-02-14 21:50:32
497Central processing unit / Computer architecture / Microprocessors / CPU cache / Cache / Microarchitecture / Parallel computing / Dynamic random-access memory / CAS latency / Computer hardware / Computer memory / Computing

Appears in the Proceedings of the 21st International Symposium on High Performance Computer Architecture (HPCA), 2015 Scaling Distributed Cache Hierarchies through Computation and Data Co-Scheduling Nathan Beckmann, Po-

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Source URL: people.csail.mit.edu

Language: English - Date: 2015-01-08 12:13:44
498Electronic engineering / Technology / Central processing unit / Microcontroller / Cyan Worlds / Texas Instruments / Semiconductor companies / Electronics / Video game developers

Report and Financial Statements06

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Source URL: www.cyantechnology-ir.com

Language: English - Date: 2007-09-11 07:00:33
499Central processing unit / Instruction set / Instruction set architectures / Instruction cycle / Optimum programming / Missile guidance / LGP-30 / D-37C / Computer architecture / Computing / Computer hardware

TIMING AND OPTlMIZATlON 8 Optimization is a programming technique which provides access to data and instructions with a minimum of nonproductive searching time. When a program is optimized for the LGP-21, the programmer

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Source URL: www.ed-thelen.org

Language: English - Date: 2008-07-23 04:19:35
500Eckert–Mauchly Award / Year of birth missing / John Mauchly / Association for Computing Machinery / J. Presper Eckert / IEEE Computer Society / ENIAC / Computer architecture / Central processing unit / Electronic engineering / Computing / Computer science

FOR IMMEDIATE RELEASE ACM AND IEEE COMPUTER SOCIETY TAP COMPUTER ARCHITECTURE INNOVATOR FOR TOP AWARD Michigan’s Trevor Mudge Developed Advances that Lower Power Consumption of Processors NEW YORK, MAY 22, ACM

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Source URL: awards.acm.org

Language: English - Date: 2014-05-22 10:23:32
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